Embedded and system-on-a-chip (SoC) systems are becoming more prevalent in the computing ecosystem. For example, a great number of SoC systems are being deployed in SoC servers in data centers. Traditional servers and SoC servers alike typically require manageability functions in order to operate. Although the manageability functions of a particular system may vary depending on the implementation, they may include, for example, integrity attestation, monitoring and logging (e.g., for malware detection or system operating condition alerts), system configuration and control, software and firmware updates, and other suitable functions. In typical SoC systems, manageability is integrated into the SoC in the form of a microcontroller having its own static random-access memory (SRAM) embedded in the SoC. Additionally, many SoCs may be placed together on a particular field replaceable unit (FRU) for fault isolation and to simplify the replacement of components.
Embedded manageability controllers (e.g., on SoCs) require memory to store code and data for operation. As the number of manageability features implemented in the manageability controllers increases, so does the demand for memory for the necessary data and code storage. Although personal computing systems are able to access host dynamic random-access memory (DRAM) for operation (e.g., via uniform memory access), manageability controllers generally cannot use system host DRAM due to reliability requirements in the server space. Accordingly, SoC-based manageability controllers are effectively limited to the use of SRAM embedded into the SoC, which creates a significant barrier to the introduction of additional manageability features. That is, the associated cost, die size, and power consumption of additional SRAM banks limit the ability to increase the size of the SRAM on the SoC, thereby limiting the number of available manageability functions on the SoC.
In an effort to improve manageability while side-stepping those physical limitations, various techniques have been employed. For example, at least one technique involves paging read-only data and code from external memory (e.g., flash memory accessed over a serial peripheral interface) into the internal SRAM. That is, the portion of the code and data that is actively used at a given point in time is copied from the external memory to the internal SRAM. However, such an approach significantly impacts performance due to reloading from the external memory. Alternatively, external DRAM accessible to the manageability controller and dedicated for its use my be embedded on the SoC; however, such an approach requires a memory controller, which significantly increases chip cost, power consumption, and complexity.